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JEDEC JESD47I.01

$36.00

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 10/01/2016

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Description

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. This is a minor editorial revision to JESD47I, published December 2015.

Product Details

Published:
10/01/2016
Number of Pages:
28
File Size:
1 file , 280 KB